The present invention relates to a semiconductor design technology, and more particularly, to a circuit for generating an output enable signal corresponding to CAS latency.
Semiconductor memory devices, including Double Data Rate Synchronous DRAM (DDR SDRAM), generally receive a read command from outside in response to an external clock signal and output data stored therein to the outside in response to an internal clock signal. When data is to be outputted, the semiconductor memory device processes the data using the internal clock signal, not the external clock signal. Here, the read command is inputted in synchronization with the external clock signal, while the data is outputted in synchronization with the internal clock signal. Therefore, the semiconductor memory devices should include a circuit for synchronizing the read command synchronized with the external clock signal with the internal clock signal. In view of the read command, the clock signal for synchronization is changed from the external clock signal to the internal clock signal, and this operation is generally called ‘domain crossing’.
Meanwhile, the semiconductor memory device is provided with an output enable signal generation circuit which performs domain crossing on the read command from the external clock signal to the internal clock signal, and generates an output enable signal depending on CAS latency information. The output enable signal is to ensure an operation that outputs data in response to the external clock signal when the read command is applied and after accounting for CAS latency. Since this signal is subjected to domain crossing, it becomes synchronized with the internal clock signal. Typically, CAS latency is stored in a mode register set provided in the semiconductor memory device, and has information indicating that the read command is applied in one cycle unit of the external clock signal and on whether data is to be outputted at what point of the external clock signal.
Further, the semiconductor memory device is provided with a Delay Locked Loop (DLL) for generating an internal clock signal, and a DLL clock signal with which the output enable signal is synchronized.
FIG. 1 is a block diagram showing a conventional output enable signal generation circuit for a semiconductor memory device. Referring to FIG. 1, the conventional output enable signal generation circuit includes an OE reset signal generator 110, a reset signal synchronizer 130, and an output enable signal output unit 150. The OE reset signal generator 110 synchronizes a reset signal RSTb with an external clock signal CLK_EXT to generate an OE reset signal RSTb_OE. Here, the reset signal RSTb is activated in response to an active operation of a semiconductor memory device, a locking operation of a DLL, and a setting operation of a mode register set. The reset signal synchronizer 130, designed with a D-flip flop, synchronizes the OE reset signal RSTb_OE with a DLL clock signal CLK_DLL to generate a source reset signal RSTb_SRC that resets the output enable signal output unit 150. The output enable signal output unit 150 is reset in response to the source reset signal RSTb_SRC, counts the external clock signal CLK_EXT and the DLL clock signal CLK_DLL to output an output enable signal OE corresponding to a read command signal RD_EN and CAS latency CL. Here, the read command signal RD_EN is a pulse signal which is activated when the read command for the semiconductor memory device is applied, and after the output enable signal output unit 150 is reset in response to the source reset signal RSTb_SRC. Thus, the output enable signal output unit 150 can generate the output enable signal OE corresponding to the read command signal RD_EN and the CAS latency CL only when the source reset signal RSTb_SRC is normally activated at a desired time.
In other words, the output enable signal output unit 150 can perform a stable operation only when the OE reset signal RSTb_OE that is outputted in synchronization with the external clock signal CLK_EXT by the OE reset signal generator 110 is outputted exactly in synchronization with the DLL clock signal CLK_DLL by the reset signal synchronizer 130. In the conventional output enable signal generation circuit, however, the source reset signal RSTb_SRC may not be synchronized with the DLL clock signal CLK_DLL.
FIGS. 2A and 2B are waveform diagrams for explaining an operation timing of an OE reset signal RSTb_OE and a DLL clock signal CLK_DLL. That is, FIG. 2A is a waveform diagram when a source reset signal RSTb_SRC is normally generated and FIG. 2B is a waveform diagram when the source reset signal RSTb_SRC is abnormally generated. For reference, tD1 and tD2 in FIGS. 2A and 2B indicate the degree of delay reflected in a DLL upon completion of locking. That is, tD1 indicates the degree of delay reflected in a variable delay circuit provided in the DLL and tD2 represents the degree of delay reflected in a delay replica model circuit provided in the DLL. In the same semiconductor memory device, tD2 is constant, while tD1 varies depending on an operating frequency.
Referring to FIGS. 1 and 2A, the OE reset signal RSTb_OE is synchronized and outputted in response to the external clock signal CLK_EXT by the OE reset signal generator 110. In FIG. 2A, there is a sufficiently secured setup time ({circle around (a)}) between the time the OE reset signal RSTb_OE transits from logic ‘low’ to logic ‘high’ and a rising edge of the DLL clock signal RCLK_DLL. Because of this, the reset signal synchronizer 130 stably synchronizes the OE reset signal RSTb_OE with the DLL clock signal CLK_DLL to output the source reset signal RSTb_SRC. As a result, the source reset signal RSTb_SRC synchronized with the DLL clock signal CLK_DLL ensures that the output enable signal output unit 150 can stably operate thereafter.
Meanwhile, referring to FIGS. 1 and 2B, the OE reset signal RSTb_OE is synchronized and outputted in response to the external clock signal CLK_EXT, as shown in FIG. 2A. In FIG. 2B, there is an insufficiently secured setup time ({circle around (b)}) between a transition time of the OE reset signal RSTb_OE and a rising edge of the DLL clock signal RCLK_DLL. Due to this, the reset signal synchronizer 130 does not stably synchronize the OE reset signal RSTb_OE with the DLL clock signal CLK_DLL. In result, this means that it is difficult to ensure that the output enable signal output unit 150 can stably operate thereafter.
As mentioned above, since the OE reset signal RSTb_OE and the DLL clock signal RCLK_DLL, which are activated in synchronization with the external clock signal CLK_EXT, do not secure a sufficient setup time, the conventional output enable signal generation circuit cannot ensure a stable operation of the output enable signal output unit 150. This means that the output enable signal output unit 150 cannot be reset at a desired time, and cannot generate an output enable signal OE corresponding to the read command signal RD_EN and the CAS latency CL. In other words, the semiconductor memory device cannot output desired data when the read command is applied and after the CAS latency CL.